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VLSI Packaging Evolution and Innovations

Hello Dear Readers,   Today in this post, I will provide some deep insight into the VLSI packaging evolution and innovations. Semiconductor packaging has evolved from a simple protective housing into a critical performance enabler. In the modern VLSI landscape, packaging is no longer an afterthought; it is a fundamental determinant of PPA (Power, Performance, and Area) metrics, often dictating the thermal limits and signal integrity of the final SoC. 1. Traditional Packaging Technologies: These methods are the workhorses of the industry, widely used for low-to-medium complexity devices where cost-efficiency is paramount. Wire Bonding (QFN, QFP, DIP): Wire bonding is the most mature interconnection technology. It uses thin gold, copper, or aluminum wires to connect the die's bond pads to the package's internal leadframe. Implementation: The die is attached face-up to a leadframe or substrate. A wire bonder uses thermocompression or ultrasonic energy to attach wires betwee...

Hardware Design Engineer at Cyient Pune

 Hello Dear Readers,

Currently at Cyient Pune vacancy for Design Hardware Design Engineer role.

Cyient is a global engineering and technology solutions company. As a Design, Build, and Maintain partner for leading organizations worldwide, we take solution ownership across the value chain to help clients focus on their core, innovate, and stay ahead of the curve. We leverage digital technologies, advanced analytics capabilities, and our domain knowledge and technical expertise, to solve complex business problems.

With over 15,000 employees globally, we partner with clients to operate as part of their extended team in ways that best suit their organization’s culture and requirements. Our industry focus includes aerospace and defence, healthcare, telecommunications, rail transportation, semiconductor, geospatial, industrial, and energy.

Job Description:

  • Knowledge of Analog & Digital circuit design
  • Knowledge of Power supply circuit design
  • Able to work with ICs & Microprocessors
  • Design on Buck-boost regulator & LDO
  • Operating voltage will be 1.5 to 5 V with a current range of 5 to 10 Amp and power dissipation around 30 to 40W
  • Knowledgeable on EMC requirements for components used for circuit design to clear the EMC test
  • Able to perform simulation using various tools (e.g PSpice)
  • Able to develop test procedures and test the electronic circuit

Skills & Experience:

Embedded Hardware, Hardware Design, Power Electronics


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