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VLSI Packaging Evolution and Innovations

Hello Dear Readers,   Today in this post, I will provide some deep insight into the VLSI packaging evolution and innovations. Semiconductor packaging has evolved from a simple protective housing into a critical performance enabler. In the modern VLSI landscape, packaging is no longer an afterthought; it is a fundamental determinant of PPA (Power, Performance, and Area) metrics, often dictating the thermal limits and signal integrity of the final SoC. 1. Traditional Packaging Technologies: These methods are the workhorses of the industry, widely used for low-to-medium complexity devices where cost-efficiency is paramount. Wire Bonding (QFN, QFP, DIP): Wire bonding is the most mature interconnection technology. It uses thin gold, copper, or aluminum wires to connect the die's bond pads to the package's internal leadframe. Implementation: The die is attached face-up to a leadframe or substrate. A wire bonder uses thermocompression or ultrasonic energy to attach wires betwee...
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Design Verification Engineer at Mulya Technologies Bangalore

 Hello Dear Readers,

Currently at Mulya Technologies Bangalore vacancy for a Design Verification Engineer role.

About the job:

Design Verification Engineers- Entry level ( Highly competitive salary ) - 3 positions

Location: Bangalore


Company Brief:


Founded by semiconductor industry veterans and modem experts and funded by leading semiconductor investors. We are an early-stage silicon and software startup revolutionizing wireless signal processing with the world's first AI enhanced, truly software defined, modular, customizable, and flexible silicon platform.


We are currently in stealth mode; stay tuned for more exciting updates in the coming months!


We are assembling a world-class team at our headquarters in San Diego and engineering design center in Bangalore to fuel our vision.


Calling on Engineers who have a background in any combination of the following areas:

Education:

Mtech in VLSI / Microelecronics from IITs / IISc / NITs / IITs / Bits / Guindy / DTU(DCE) / NSUT (NSIT ) / Thapar / PEC / Jadavpur / Shibpur / COEP etc

  • ASIC Design and Verification
  • SoC Design
  • Processor (CPU/DSP) architecture

Desirable Skills:

experience in verification. (academic projects/ Industrial internship/internship- post-qualification)


Staff Engineer ( IP / SOC Verification )

  • 0-1 yrs Industry experience 
  • SV and UVM 
  • C language 
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