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VLSI Packaging Evolution and Innovations

Hello Dear Readers,   Today in this post, I will provide some deep insight into the VLSI packaging evolution and innovations. Semiconductor packaging has evolved from a simple protective housing into a critical performance enabler. In the modern VLSI landscape, packaging is no longer an afterthought; it is a fundamental determinant of PPA (Power, Performance, and Area) metrics, often dictating the thermal limits and signal integrity of the final SoC. 1. Traditional Packaging Technologies: These methods are the workhorses of the industry, widely used for low-to-medium complexity devices where cost-efficiency is paramount. Wire Bonding (QFN, QFP, DIP): Wire bonding is the most mature interconnection technology. It uses thin gold, copper, or aluminum wires to connect the die's bond pads to the package's internal leadframe. Implementation: The die is attached face-up to a leadframe or substrate. A wire bonder uses thermocompression or ultrasonic energy to attach wires betwee...
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ASIC Engineer at NVIDIA Bangalore

  Hello Dear Readers,

Currently at Nvidia Bangalore vacancy for an ASIC Engineer role.

NVIDIA is seeking elite ASIC Low power Design and Verification engineers to work on the design, implementation, and verification of low-power features for the world’s leading SoCs and GPUs. This position offers the opportunity to have real impact in a dynamic, technology-focused company impacting product lines ranging from consumer graphics to self-driving cars and the growing field of artificial intelligence. We have crafted a team of outstanding people stretching around the globe, whose mission is to push the frontiers of what is possible today and define the platform for the future of computing. At NVIDIA, our employees are passionate about parallel and visual computing. We're united in our quest to transform the way graphics are used to solve some of the most complex problems in computer science.

The GPU started out as an engine for simulating human imagination, conjuring up the amazing virtual worlds of video games and Hollywood films. Today, NVIDIA’s GPU simulates human intelligence, running deep learning algorithms and acting as the brain of computers, robots, and self-driving cars that can perceive and understand the world. NVIDIA is increasingly known as “the AI computing company.”

What you’ll be doing:

  • Work on design, implementation and verification of low power aspects of NVIDIA’s family of chips

  • Come up with micro-architecture, implement RTL, and verify the implementation of a variety of low power features, and deliver a fully verified, synthesis/timing clean design

  • Collaborate with architects, designers, pre- and post-silicon verification teams, synthesis, timing and back-end teams to accomplish your tasks.

  • Collaborate with system level and unit level teams to cover the features well from functional, electrical, performance, and noise aspects.

  • Validate the effectiveness of the low power features on silicon

  • Architecture, development and correlation of power estimation models/tools for NVIDIA's chips

  • Help architect and develop power models for use-cases, Idle power and IO power.

  • Chip in to design the tools based on these models and their testing methodology/infrastructures

  • Correlate and Calibrate the power models using measured silicon data

  • Analyze and help decide the chip configuration and process technology options to optimize power/performance for NVIDIA's upcoming chips

  • Help study and contribute to Performance/Watt improvement ideas for NVIDIA's GPUs and SOCs

What we need to see:

  • BS/MS or equivalent experience with specialization related to Low Power techniques, implementation and Verification.

  • 2+ years of experience.

  • Experience in micro-architecture and RTL development of complex designs

  • Mastery of ASIC design flow including RTL design, verification, logic synthesis, prototyping, DFT, timing analysis, floor planning, ECO, bring-up & lab debug

  • Strong fundamentals in power including transistor-level leakage/dynamic characteristics of VLSI circuits

  • Good understanding of low power design techniques such as multi VT, Clock gating, Power gating, and Dynamic Voltage-Frequency Scaling (DVFS)

  • Experience in Low Power verification flow and tools (UPF/CPF formats, and VCLP/MVRC, NLP/MVSIM or similar tools)

  • Experience in design and verification tools (VCS or equivalent simulation tools, Debussy, GDB and other debug tools)

  • Strong fundamentals in power including transistor-level leakage/dynamic characteristics of VLSI circuits

  • Familiarity with low power design techniques such as multi VT, Clock gating, Power gating, and Dynamic Voltage-Frequency Scaling (DVFS)

  • Strong background in power estimation techniques, flows and algorithms

  • Good programming skills - Python preferred. Good skills with object-oriented programming and design.

Ways to stand out from the crowd:

  • Good software programming skills. Python/Perl/C++ preferred.

  • Confident debugging and problem-solving skills.

  • Good communication skills and ability & desire to work as a great teammate.



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