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Design Engineer - STA, SD, Power, PDN at Dew Software

Hello Dear Readers,   Currently at Dew Software Bangalore vacancy for Design Engineer - STA, SD, Power, PDN role. Dew Software, a leading player in the Digital Transformation space, is seeking a skilled Design Engineer specializing in STA (Static Timing Analysis), SD (Signal Integrity), Power, and PDN (Power Delivery Network) to join our team. Working with Fortune 500 companies to support their digital innovation and transformation strategies, the Design Engineer will be responsible for ensuring the integrity and efficiency of digital designs through comprehensive analysis and optimization. Dew Software is dedicated to delivering exceptional outcomes with cutting-edge technologies, and this is an excellent opportunity to contribute to the growth and success of our clients. Responsibilities: Perform STA (Static Timing Analysis) to ensure design meets timing requirements Conduct signal integrity analysis to optimize signal integrity and minimize signal integrity issues Provide power anal
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ASIC Design Verification Engineer at Juniper Networks

 Hello Dear Readers,

Currently, at Juniper Networks Banglore vacancy for an ASIC Design Verification Engineer role.

Juniper is a leading provider of advanced routers and switches for the internet. We keep the world connected with speed, reliability, security, and ease of use. We believe in excellence and we strive to achieve that through employee motivation, training, and teamwork within a collaborative and innovative culture.

Want to be a part of a fast-paced team responsible for delivering high-speed ASICs for large, complex systems? Our team at Silicon Systems Technology Group (SST) is seeking ASIC Verification Engineers to verify the next generation of ASICs for new core routers, switches, and firewalls. We are looking to hire sharp individuals with excellent communication, problem-solving, and leadership skills.


Responsibilities:

  • You will be exposed to the latest verification methodologies like UVM and enable complex feature verification suites.
  • Architect and Develop block level verification environments for sub-system and full-chip using System Verilog and UVM methodology. (30%)
  • Define, architect, code, and deliver verification suites/tests for ASICs that enable faster, denser, feature-rich systems. Use various front-end simulator tools (VCS/NC) to perform this activity. (25%)
  • Verify large ASIC blocks independently and rapidly and sign off them for tape-out with analysis of code coverage, functional coverage, and Gate level simulation. (30%)
  • Work closely with logic designers to resolve bugs and software developers to assist in software and bring-up development. (10%)
  • Develop Perl, Python and/or shell scripts to improve current verification infrastructure/methodology (5%)

Required Skills:

  • ASIC Verification using SystemVerilog
  • Experience in constrained-random verification is a strong plus
  • Experience with verification methodology like OVM/VMM/UVM
  • Perl/Tcl scripting is strongly preferred
  • Experience verifying networking protocols such as Ethernet is desirable
  • Strong problem-solving and ASIC debugging skills
  • MSEE or BSEE is required with at least +/-years of ASIC Verification Experience.

Comments

  1. Anonymous26 November 2022 at 19:30

    Hi bro I am shortlisted and got a interview call thanks for your resume building tips

    ReplyDelete

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