Hello Dear Readers, Today in this post, I will provide some deep insight into the VLSI packaging evolution and innovations. Semiconductor packaging has evolved from a simple protective housing into a critical performance enabler. In the modern VLSI landscape, packaging is no longer an afterthought; it is a fundamental determinant of PPA (Power, Performance, and Area) metrics, often dictating the thermal limits and signal integrity of the final SoC. 1. Traditional Packaging Technologies: These methods are the workhorses of the industry, widely used for low-to-medium complexity devices where cost-efficiency is paramount. Wire Bonding (QFN, QFP, DIP): Wire bonding is the most mature interconnection technology. It uses thin gold, copper, or aluminum wires to connect the die's bond pads to the package's internal leadframe. Implementation: The die is attached face-up to a leadframe or substrate. A wire bonder uses thermocompression or ultrasonic energy to attach wires betwee...
Hello Dear Readers,
Currently, Google Bangalore has a vacancy for an ASIC Design for Testability Engineer.
Minimum qualifications:
- Bachelor's degree in Electrical Engineering or equivalent practical experience.
- Experience with ATPG, LV, BIST, JTAG tools and flow.
- Experience in DFT of IPs (e.g., CPU, GPU, DDR).
Preferred qualifications:
- Knowledge of high-performance design DFT techniques.
- Ability to scale DFT, with a focus on minimal area overhead.
- Understanding of the end-to-end flows of Design, Verification, DFT, and PD.
- Proficient with a scripting language such as Perl.
- Proficient with Synthesis, Lint, CDC, LEC and DFT timing, and STA.
Responsibilities:
- Work on a team of DFT engineers, working closely with RTL and Physical Designer engineers.
- Write basic to complex scripts to automate the DFT flow.
- Develop tests that can be used for Production in the ATE flow.
- Communicate and work with multi-disciplined and multi-site teams.
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