Hello Dear Readers, Texas Instruments Bangalore has a vacancy for the Physical Design Engineer role. We need an Physical Design Methodology Engineer to join our ATD team. The candidate should have a strong background in back-end design of ASIC/SoC chips. The ideal candidate will have a bachelor’s or master’s degree in Electrical Engineering or a related field. Requirements: 1 - 2 Years of experience in physical design Bachelor’s or master’s degree in Electrical/Electronics Engineering or a related field Strong understanding of physical design principles Must know the basics of floorplan, placement, CTS, routing, ECO, Physical Verification Proficiency in back-end design tools, such as Cadence Genus/Innovus/Tempus/Voltus Excellent problem-solving skills and attention to detail Effective communication and collaboration skills Responsibilities: Synthesis to GDSII Perform full Physical design flow and its verification Work closely with Digital Design and DFT engineers Ensure...
Hello Dear Readers,
Currently, Google Bangalore has a vacancy for an ASIC Design for Testability Engineer.
Minimum qualifications:
- Bachelor's degree in Electrical Engineering or equivalent practical experience.
- Experience with ATPG, LV, BIST, JTAG tools and flow.
- Experience in DFT of IPs (e.g., CPU, GPU, DDR).
Preferred qualifications:
- Knowledge of high-performance design DFT techniques.
- Ability to scale DFT, with a focus on minimal area overhead.
- Understanding of the end-to-end flows of Design, Verification, DFT, and PD.
- Proficient with a scripting language such as Perl.
- Proficient with Synthesis, Lint, CDC, LEC and DFT timing, and STA.
Responsibilities:
- Work on a team of DFT engineers, working closely with RTL and Physical Designer engineers.
- Write basic to complex scripts to automate the DFT flow.
- Develop tests that can be used for Production in the ATE flow.
- Communicate and work with multi-disciplined and multi-site teams.
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