Hello Dear Readers, Currently at Dew Software Bangalore vacancy for Design Engineer - STA, SD, Power, PDN role. Dew Software, a leading player in the Digital Transformation space, is seeking a skilled Design Engineer specializing in STA (Static Timing Analysis), SD (Signal Integrity), Power, and PDN (Power Delivery Network) to join our team. Working with Fortune 500 companies to support their digital innovation and transformation strategies, the Design Engineer will be responsible for ensuring the integrity and efficiency of digital designs through comprehensive analysis and optimization. Dew Software is dedicated to delivering exceptional outcomes with cutting-edge technologies, and this is an excellent opportunity to contribute to the growth and success of our clients. Responsibilities: Perform STA (Static Timing Analysis) to ensure design meets timing requirements Conduct signal integrity analysis to optimize signal integrity and minimize signal integrity issues Provide power anal
Hello Dear Readers,
Currently, Google Bangalore has a vacancy for an ASIC Design for Testability Engineer.
Minimum qualifications:
- Bachelor's degree in Electrical Engineering or equivalent practical experience.
- Experience with ATPG, LV, BIST, JTAG tools and flow.
- Experience in DFT of IPs (e.g., CPU, GPU, DDR).
Preferred qualifications:
- Knowledge of high-performance design DFT techniques.
- Ability to scale DFT, with a focus on minimal area overhead.
- Understanding of the end-to-end flows of Design, Verification, DFT, and PD.
- Proficient with a scripting language such as Perl.
- Proficient with Synthesis, Lint, CDC, LEC and DFT timing, and STA.
Responsibilities:
- Work on a team of DFT engineers, working closely with RTL and Physical Designer engineers.
- Write basic to complex scripts to automate the DFT flow.
- Develop tests that can be used for Production in the ATE flow.
- Communicate and work with multi-disciplined and multi-site teams.
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