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Physical Design Methodology Engineer at Texas Instruments

  Hello Dear Readers, Texas Instruments Bangalore has a vacancy for the Physical Design Engineer role. We need an Physical Design Methodology Engineer to join our ATD team. The candidate should have a strong background in back-end design of ASIC/SoC chips. The ideal candidate will have a bachelor’s or master’s degree in Electrical Engineering or a related field. Requirements: 1 - 2 Years of experience in physical design Bachelor’s or master’s degree in Electrical/Electronics Engineering or a related field Strong understanding of physical design principles Must know the basics of floorplan, placement, CTS, routing, ECO, Physical Verification Proficiency in back-end design tools, such as Cadence Genus/Innovus/Tempus/Voltus Excellent problem-solving skills and attention to detail Effective communication and collaboration skills Responsibilities: Synthesis to GDSII Perform full Physical design flow and its verification Work closely with Digital Design and DFT engineers Ensure...
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Physical Design Engineer at NVIDIA

  Hello Dear Readers,

Currently at Nvidia Bangalore vacancy for Physical Design Engineer role.

NVIDIA is seeking passionate, highly motivated, and creative design engineers to be part of a team working on industry-leading GPUs and SOCs. This position offers the opportunity to have real impact in a dynamic, technology-focused company impacting product lines ranging from consumer graphics to self-driving cars and the growing field of artificial intelligence. We have crafted a team of exceptional people stretching around the globe, whose mission is to push the frontiers of what is possible today and define the platform for the future of computing.

What you'll be doing:

  • In this position, you will be expected to lead all block/chip level PD activities.

  • PD activities includes floor plans, abstract view generation, RC extraction, PNR, STA, EM,IR DROP, DRCs & schematic to layout verification. Work in collaboration with design team for addressing design challenges.

  • Help team members in debugging tool/design related issues.

  • Constantly look for improvement in RTL2GDS flow to improve PPA. Troubleshoots a wide variety up to and including difficult design issues and applied proactive intervention.

  • Responsible for all aspects of physical design and implementation of GPU and other ASICs targeted at the desktop, laptop, workstation, and mobile markets.

What we need to see:

  • BE/BTECH/MTECH, or equivalent experience.

  • 2+ years of experience in Physical Design.

  • Strong understanding of the RTL2GDSII flow or design implementation in leading process technologies. Good understanding of the RTL2GDSII concepts related to synthesis, place & route, CTS, timing convergence, and layout closure.

  • Expertise in high-frequency design methodologies. Good knowledge and experience in Block-level and Full-chip Floor-planning and Physical verification. Working experience with tools like ICC2/Innovus, Primetime/Tempus, etc, used in the RTL2GDSII implementation.

  • Strong knowledge and experience in the standard place and route flow ICC2/Synopsys and Innovus/Cadence flow preferred. Well-versed with timing constraints, STA, and timing closure.

  • Good automation skills in PERL, TCL, tool specific scripting on one of the industry-leading Place & Route tools.

  • Ability to multi-task and flexibility to work in a global environment.

  • Good communication skills and strong motivation, Strong analytical & Problem-solving skills. Proficiency using Perl, Tcl, and Make scripting is preferred.


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