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YAML in Semiconductor EDA: From Configuration Language to Reusable Design-Flow Methodology

Hello Dear Readers,   Today in this post, I will provide some deep insight about yaml langauge for CAD flow developments with detailed examples. YAML is not a programming language in the same sense as Python, Tcl, C++, or Verilog. It is primarily a human-readable data serialization/configuration language . In semiconductor EDA, that distinction is important because YAML generally describes what a flow should do , while Python/Tcl/Shell and the EDA tools execute the flow . The official YAML specification describes it as a data serialization language designed to be human-friendly and portable across programming languages. For the semiconductor angle, this becomes particularly interesting because YAML can act as a configuration layer between design methodology and EDA implementation . Frameworks such as Hammer explicitly use YAML/JSON configuration and an intermediate representation to standardize information exchanged between design, technology, and tool plugins. 1. Introduction M...
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Engineer I - Verification at Microchip Bangalore

 Hello Dear Readers, 

Currently at Microchip Bangalore vacancy for Engineer I - Verification role.

Job Description:

  • Define and develop verification architecture
  • Define and develop verification methodologies
  • Define and develop verification environments
  • Write verification specifications, verification plans, and documentation
  • Generate test bench and automatic regression plans
  • Be responsible for verification architecture, simulations, verifications, and debugging of circuit and logic designs
  • Complete block-level verification and chip level verification
  • Bring a self-motivated and enthusiastic approach that will achieve any new requirements and overcome all challenges
  • Able to debug the RTL for design intent and Interface with cross-functional teams and collaboration in all verification related activities
  • Mentor Junior Engineers on need basis
 

Requirements/Qualifications:

  • Master's degree in VLSI design.
  • Languages (Must) : Verilog and System Verilog.
  • Methodologies (Any one) : OVM, VMM., UVM.
  • EDA Tools (One of them is must): Questasim, VCS, NCSim, NCVerilog.
  • Good understanding of digital design fundamentals.
  • Proficient with Unix environment and common scripting languages.
  • Expertise in test plan development. 
  • Expertise in Functional / Code Coverage activity.
  • Experience in IP level verification activities.
  • Hands on project experience in coverage/assertion driven verification 
  • Testbench development in Verilog/SystemVerilog using verification methodology
  • Strong in simulation and debugging skills..
  • Good knowledge of AMBA protocols like APB,AHB and AXI.
  • Knowledge of revision control tools like CVS and GIT.
  • Should be able to handle tasks independently.
  • Good communication skills and the ability to work in a team environment. 
  • Experience with processor-based verification.
  • Experience in UVM methodology.

Travel Time:

0% - 25%


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