Hello Dear Readers, Currently at Dew Software Bangalore vacancy for Design Engineer - STA, SD, Power, PDN role. Dew Software, a leading player in the Digital Transformation space, is seeking a skilled Design Engineer specializing in STA (Static Timing Analysis), SD (Signal Integrity), Power, and PDN (Power Delivery Network) to join our team. Working with Fortune 500 companies to support their digital innovation and transformation strategies, the Design Engineer will be responsible for ensuring the integrity and efficiency of digital designs through comprehensive analysis and optimization. Dew Software is dedicated to delivering exceptional outcomes with cutting-edge technologies, and this is an excellent opportunity to contribute to the growth and success of our clients. Responsibilities: Perform STA (Static Timing Analysis) to ensure design meets timing requirements Conduct signal integrity analysis to optimize signal integrity and minimize signal integrity issues Provide power anal
Hello Dear Readers,
Currently at Microchip Bangalore vacancy for Engineer I - Verification role.
Job Description:
- Define and develop verification architecture
- Define and develop verification methodologies
- Define and develop verification environments
- Write verification specifications, verification plans, and documentation
- Generate test bench and automatic regression plans
- Be responsible for verification architecture, simulations, verifications, and debugging of circuit and logic designs
- Complete block-level verification and chip level verification
- Bring a self-motivated and enthusiastic approach that will achieve any new requirements and overcome all challenges
- Able to debug the RTL for design intent and Interface with cross-functional teams and collaboration in all verification related activities
- Mentor Junior Engineers on need basis
Requirements/Qualifications:
- Master's degree in VLSI design.
- Languages (Must) : Verilog and System Verilog.
- Methodologies (Any one) : OVM, VMM., UVM.
- EDA Tools (One of them is must): Questasim, VCS, NCSim, NCVerilog.
- Good understanding of digital design fundamentals.
- Proficient with Unix environment and common scripting languages.
- Expertise in test plan development.
- Expertise in Functional / Code Coverage activity.
- Experience in IP level verification activities.
- Hands on project experience in coverage/assertion driven verification
- Testbench development in Verilog/SystemVerilog using verification methodology
- Strong in simulation and debugging skills..
- Good knowledge of AMBA protocols like APB,AHB and AXI.
- Knowledge of revision control tools like CVS and GIT.
- Should be able to handle tasks independently.
- Good communication skills and the ability to work in a team environment.
- Experience with processor-based verification.
- Experience in UVM methodology.
Travel Time:
0% - 25%
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