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Physical Design/PDK methodology Engineer

Hello Dear Readers, At Applied Materials Bangalore, there is a vacancy for a Physical Design/PDK methodology Engineer role. Applied Materials is a global leader in materials engineering solutions used to produce virtually every new chip and advanced display in the world. We design, build and service cutting-edge equipment that helps our customers manufacture display and semiconductor chips – the brains of devices we use every day. As the foundation of the global electronics industry, Applied enables the exciting technologies that literally connect our world – like AI and IoT. If you want to push the boundaries of materials science and engineering to create next generation technology, join us to deliver material innovation that changes the world.  Key Responsibility: Expertise in PDK enablement and library  validation/automation. Hands-on experience with LVS/Parasitic extraction/standard cell characterization flows and methodologies Design/System level experience with DTCO and ...
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Engineer I - Verification at Microchip Bangalore

 Hello Dear Readers, 

Currently at Microchip Bangalore vacancy for Engineer I - Verification role.

Job Description:

  • Define and develop verification architecture
  • Define and develop verification methodologies
  • Define and develop verification environments
  • Write verification specifications, verification plans, and documentation
  • Generate test bench and automatic regression plans
  • Be responsible for verification architecture, simulations, verifications, and debugging of circuit and logic designs
  • Complete block-level verification and chip level verification
  • Bring a self-motivated and enthusiastic approach that will achieve any new requirements and overcome all challenges
  • Able to debug the RTL for design intent and Interface with cross-functional teams and collaboration in all verification related activities
  • Mentor Junior Engineers on need basis
 

Requirements/Qualifications:

  • Master's degree in VLSI design.
  • Languages (Must) : Verilog and System Verilog.
  • Methodologies (Any one) : OVM, VMM., UVM.
  • EDA Tools (One of them is must): Questasim, VCS, NCSim, NCVerilog.
  • Good understanding of digital design fundamentals.
  • Proficient with Unix environment and common scripting languages.
  • Expertise in test plan development. 
  • Expertise in Functional / Code Coverage activity.
  • Experience in IP level verification activities.
  • Hands on project experience in coverage/assertion driven verification 
  • Testbench development in Verilog/SystemVerilog using verification methodology
  • Strong in simulation and debugging skills..
  • Good knowledge of AMBA protocols like APB,AHB and AXI.
  • Knowledge of revision control tools like CVS and GIT.
  • Should be able to handle tasks independently.
  • Good communication skills and the ability to work in a team environment. 
  • Experience with processor-based verification.
  • Experience in UVM methodology.

Travel Time:

0% - 25%


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