Hello Dear Readers, Today in this post I will be providing you a complete Verilog code of 4 Bit BCD Adder using the Full Adder instant model. So before the start, the code keep in mind the algorithms for the BCD adder is if the additional sum is greater than 9 will become up then we add 6 on it to make a valid BCD number so here in my code I have used this algorithm so keep in mind. Verilog Code: module bcd_4bit(input [3:0] x,y,input cy_in,output [3:0] sum,output carry,output [4:0] bcd_sum); add4 a1 (carry,sum,x,y,cy_in); assign bcd_sum=carry==1?{carry,(sum+4'b0110)}:sum; endmodule module add4(cy4,sum,x,y,cy_in     ); input [3:0] x,y; input cy_in; output [3:0] sum; output cy4; wire [2:0] carry_out; add b0(carry_out[0],sum[0],x[0],y[0],cy_in); add b1(carry_out[1],sum[1],x[1],y[1],carry_out[0]); add b2(carry_out[2],sum[2],x[2],y[2],carry_out[1]); add b3(cy4,sum[3],x[3],y[3],carry_out[2]); endmodule module add(carry_out,sum,a,b,cy_in     ); input a,b,cy_in; outpu...

  Hello Dear Readers, Here I have designed a 4 tap FIR filter using Verilog languages and some parts of the Python language to just print the input and output samples that are generating Verilog HDL. So Let's see the Code of the complete system. So first of all FIR filter is a system which transfer function has a finite number of impulsive points corresponding to the type of the filters such as high pass, low pass, bandpass, etc... so it has generally two types of structure as shown in the below, FIR Filter Structures: Here I have used the first structure in which first multiply input samples with impulse responses so without delay products is available now we give delays to that data means here we have implemented shifted adder for MAC operation of the digital filter. Verilog Code: module fir_4tap(input Clk,input signed [7:0] Xin,output reg signed [15:0] Yout);     //Internal variables. wire signed   [7:0] H0,H1,H2,H3; wire signed   [15:0] MCM_bl...

  Hello Dear Readers, First of all thanks for giving motivation on my first of designing microprocessor.  DESIGN OF THE SINGLE CYCLE MICROPROCESSOR USING VERILOG HDL . So now in this post, i will explain the 3 stages of the pipeline microprocessors namely the Fetch Unit , Decode Unit , and Execute Unit . So Let's start designing based on the specification given below. Stage-1: Fetch Unit Fetch Unit comprises half-word addressable instruction memory. It takes PC as input and gives the instruction as an output. PC is also incremented by PC=PC+1. Stage-2: Decode Unit Decode Unit reads the fetched instruction and decodes the address of two source operands and destination register. Also, it generates the immediate data. Register Bank reads the value of source operands (Rs1 and Rs2) at negative level of the clock, and writes the data in the destination register (Rd) at positive level of clock. Control Unit uses 4-bit opcode bits to determine the type of instruction.  Stage-3: E...

Hello Dear Readers, Here I have uploaded my designed single cycle 8-bit CISC microprocessor using Verilog HDL. So Let's see and try your own as per your specification.   First of all, as we know CISC microprocessor has separate instruction memory and data memory so here I have make two text file for that and then designed one by one block of the microprocessor such as clock generation, ALU(Arithmetic Logical Unit), File reading as well as writing back, ...etc. Verilog Code: module microprocessor1(); reg reset; reg clock; reg [7:0] Dmem[0:255];// data memory array for the data file stored reg [31:0] Imem[0:255];// instruction memory array for the instruction stored reg [7:0] pc; // 8-bit program counter reg [31:0] instruction; // 32-bit Instruction Register reg [7:0] opcode; // 8-bit opcode reg [7:0] destAddr; // 8-bit Destination Address reg [7:0] src1Addr; // 8-bit Source Address #1 reg [7:0] src2Addr; // 8-bit Source Address #2 reg [7:0] src1Data; // 8-bit Source Data #1 reg [7:...