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Functions And Tasks In Verilog

Hello Dear Readers, Today, I will explain how functions and tasks are used in Verilog to make our lengthy code highly optimized. Task and functions are used in the Verilog to describe the commonly used functional behavior. Instead of replicating the same code at different places, it is good and common practice to use the functions or tasks depending on the requirement. For easy maintenance of the code, it is better to use the functions or tasks like the subroutine. Let's see the example below for a better understanding. 1). Counting 1’s from the Given String Using Functions: The following are the key important points that need to remember while using the function: 1. Function can not consists of the time control statements and even delay operators. 2. Function can have at least one input argument declaration. 3. Function can consist of function calls but function cannot consist of the task. 4. Function executes in zero simulation time and returns a single value when called.

Internally Generated Clocks & Gated Clocks Modelling Using Verilog HDL

Hello Dear Readers, Today, I will explain how one can modeling an Internally and Gated clock using Verilog HDL. 1). Internally Generated Clocks: Internally generated clock signals use a system or master clock and generate output as an internally generated clock signal. But, internally generated clock signals need to be avoided as it causes the functional and timing issues in the design. The functional and timing problems are due to the combinational logic propagation delays. The internally generated clock signals can generate a glitch or spike in the output. This can trigger the sequential logic multiple times or can generate undesired output. Even due to violation of setup or hold time these types of designs have timing violations. It is always recommended to generate the internal clocks by using register output logic. But still due to the propagation delay of the flip-flop, the overall cumulative delay or skew can generate glitches or spikes in the design. As shown below, Verilog

Different types of Counters In Verilog HDL

Hello Dear Readers, Today, I will explain Designing of the different types of counters. There are two types of counter based on the how clock signal is assigned to it namely 1). Synchronous Counters 2). Asynchronous Counter. 1). Synchronous Counters: If all the storage elements are triggered by the same source clock signal then the design is said to be synchronous. The advantage of the synchronous design is the overall propagation delay for the design is equal to the propagation delay of the flip-flop or storage element. STA is very easy for the synchronous logic and even performance improvement is possible by using the pipelining. Most of the ASIC implementation uses synchronous logic. In practical applications counters are used as a clock divider network. Even counters are used in the frequency synthesizers to generate variable frequency outputs. i) Parameterized N Bit Up Counter: Counters are used to generate the predefined and required count sequence on the active edge of the c

Verilog : always@ Blocks

Hello Dear Readers, Today In this post I will explain various flavors of the always@ blocks. There are normally two ways that we normally noticed in different Verilog codes that always@( * ) and always@(posedge Clock) block. always@ blocks are used to describe events that should happen under certain conditions. always@ blocks are always followed by a set of parentheses, a begin , some code, and an end . Program 1 shows a skeleton always@ block. In Program 1 , The contents of the always@ block, namely elements describe elements that should be set when the sensitivity list is “satisfied.” For now, just know that when the sensitivity list is “satisfied,” the elements inside the always@ block are set/updated. They are not otherwise. Elements in an always@ block are set/updated sequentially and in parallel, depending on the type of assignment used. There are two types of assignments: <= (non-blocking) and = (blocking) . Non-blocking assignments happen in parallel. In other

Restoring And Non Restoring Division Algorithms Using Verilog HDL

Hello Dear Readers, Today In this post I have implemented Restoring Division Algorithm Using Verilog HDL. So I have followed this One video from Tutorial Point Youtube Channel So go through it before Verilog code. start means the start of the division; busy indicates that the divider is busy (cannot start a new division); ready indicates that the quotient and remainder are available, and the count is the output of a counter that is used to control the iterations of the division. Verilog Code(Restoring): module divider_32(a,b,start,clk,reset,q,r,busy,ready,count); input [31:0] a; // dividend input [15:0] b; // divisor input start; // start input clk,reset; // clk,reset output [31:0] q; // quotient output [15:0] r; // remainder output reg busy; // busy output reg ready; // ready output [4:0] count; // counter reg [31:0] reg_q; reg [15:0] reg_r; reg [15:0] reg_b; reg [4:0] count; wire [16:0] sub_out = {reg_r,reg_q[31]} - {1'b0,reg_b}; // sub wi

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