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YAML in Semiconductor EDA: From Configuration Language to Reusable Design-Flow Methodology

Hello Dear Readers,   Today in this post, I will provide some deep insight about yaml langauge for CAD flow developments with detailed examples. YAML is not a programming language in the same sense as Python, Tcl, C++, or Verilog. It is primarily a human-readable data serialization/configuration language . In semiconductor EDA, that distinction is important because YAML generally describes what a flow should do , while Python/Tcl/Shell and the EDA tools execute the flow . The official YAML specification describes it as a data serialization language designed to be human-friendly and portable across programming languages. For the semiconductor angle, this becomes particularly interesting because YAML can act as a configuration layer between design methodology and EDA implementation . Frameworks such as Hammer explicitly use YAML/JSON configuration and an intermediate representation to standardize information exchanged between design, technology, and tool plugins. 1. Introduction M...
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Field Application Engineer at Prodigy Technovations

 Hello Dear Readers, 

Currently at Prodigy Technovations Pvt Ltd vacancy for Field Application Engineer role.


Job Description:

Responsible for pre and post sales activities such as understanding FPGA/ASIC flow based on customer requirements, recommending technical solution and arranging demonstration of the technical solution.


Education Qualification:

You should possess a B.E/B.Tech or Master's degree in Engineering in Electronics field with a major in relevant discipline

Experience/Skills:

  • Should have experience in developing C, VHDL+ Verilog +SV +UVM methodologies
  • Understanding of ASIC/FPGA/SOC is must
  • Hands- on experience with any simulator is a must.
  • Hands-on experience with any of FPGA Implementation phases and programming is a must.
  • Design testing and Verification/Methodology is plus
  • Designing, coding and debugging applications in various software languages is a plus.
  • Trouble shooting skills
  • Organizational skills
  • Object-oriented programming (OOP)/C++ is a plus
  • Generation of Code coverage from testbench is a plus
  • Experience/Understanding with ASIC /FPGA Design Rule Checking and Verification methodologies is a plus.











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