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Physical Design Methodology Engineer at Texas Instruments

  Hello Dear Readers, Texas Instruments Bangalore has a vacancy for the Physical Design Engineer role. We need an Physical Design Methodology Engineer to join our ATD team. The candidate should have a strong background in back-end design of ASIC/SoC chips. The ideal candidate will have a bachelor’s or master’s degree in Electrical Engineering or a related field. Requirements: 1 - 2 Years of experience in physical design Bachelor’s or master’s degree in Electrical/Electronics Engineering or a related field Strong understanding of physical design principles Must know the basics of floorplan, placement, CTS, routing, ECO, Physical Verification Proficiency in back-end design tools, such as Cadence Genus/Innovus/Tempus/Voltus Excellent problem-solving skills and attention to detail Effective communication and collaboration skills Responsibilities: Synthesis to GDSII Perform full Physical design flow and its verification Work closely with Digital Design and DFT engineers Ensure...
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Field Application Engineer at Prodigy Technovations

 Hello Dear Readers, 

Currently at Prodigy Technovations Pvt Ltd vacancy for Field Application Engineer role.


Job Description:

Responsible for pre and post sales activities such as understanding FPGA/ASIC flow based on customer requirements, recommending technical solution and arranging demonstration of the technical solution.


Education Qualification:

You should possess a B.E/B.Tech or Master's degree in Engineering in Electronics field with a major in relevant discipline

Experience/Skills:

  • Should have experience in developing C, VHDL+ Verilog +SV +UVM methodologies
  • Understanding of ASIC/FPGA/SOC is must
  • Hands- on experience with any simulator is a must.
  • Hands-on experience with any of FPGA Implementation phases and programming is a must.
  • Design testing and Verification/Methodology is plus
  • Designing, coding and debugging applications in various software languages is a plus.
  • Trouble shooting skills
  • Organizational skills
  • Object-oriented programming (OOP)/C++ is a plus
  • Generation of Code coverage from testbench is a plus
  • Experience/Understanding with ASIC /FPGA Design Rule Checking and Verification methodologies is a plus.











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