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VLSI Packaging Evolution and Innovations

Hello Dear Readers,   Today in this post, I will provide some deep insight into the VLSI packaging evolution and innovations. Semiconductor packaging has evolved from a simple protective housing into a critical performance enabler. In the modern VLSI landscape, packaging is no longer an afterthought; it is a fundamental determinant of PPA (Power, Performance, and Area) metrics, often dictating the thermal limits and signal integrity of the final SoC. 1. Traditional Packaging Technologies: These methods are the workhorses of the industry, widely used for low-to-medium complexity devices where cost-efficiency is paramount. Wire Bonding (QFN, QFP, DIP): Wire bonding is the most mature interconnection technology. It uses thin gold, copper, or aluminum wires to connect the die's bond pads to the package's internal leadframe. Implementation: The die is attached face-up to a leadframe or substrate. A wire bonder uses thermocompression or ultrasonic energy to attach wires betwee...
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Design IP Verification Engineer II at Cadence Design System

 Hello Dear Readers,

Currently, at Cadence Banglore, Noida vacancy for Design IP Verification Engineer II role.

Job Description: 

Design Verification Engineer for IP development team.


  • Verification role for Serial and Interface Design IPs verification (PCIe, CCIX, CXL, USB, Ethernet, SATA/SAS, UFS, SPI, HDMI, MIPI, I3C)
  • UVM testbench development to build a robust, scalable and efficient testbench to verify the design IPs.
  • In addition to UVM functional verification, the role could involve Formal verification of complex design modules.
  • In addition to UVM functional verification, role could involve participating in Emulation qualification of design IPs.
  • Understand design and produce detailed verification strategy and test plan.
  • Self-starter and learner with passion for getting the job done on time with great quality.
  • Strong problem solving, analytical and debug skills
  • Excellent verbal and written communications skills
  • Clearly communicate project status, issues etc.

Position Requirements:

  • BE/BTech/ME/MTech - Electrical / Electronics / VLSI with an experience as a design and verification engineer.
  • Strong background on functional verification fundamentals, environment planning, test plan generation, environment development is a must.
  • Design Verification experience verifying complex designs and leading projects from concept to verification closure.
  • Strong hands-on UVM and System Verilog coding experience and functional verification environment development is required.
  • Experience working on verifying any Serial IP or Interface protocols (PCIe, CCIX, CXL, USB, Ethernet, SATA/SAS, UFS, SPI, HDMI, MIPI, I3C)
  • Formal verification and/or Emulation experience is highly desirable.

  • AMBA protocol (AXI5, CHI, CXS) experience is desirable.
  • Familiarity with using 3rd party VIPs, Cadence preferred.
  • Team player with strong communication skills, and ability to work independently on the verification of a portion of the design.
  • Prior experience in IP development teams would be an added advantage.


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