Hello Dear Readers, Texas Instruments Bangalore has a vacancy for the Physical Design Engineer role. We need an Physical Design Methodology Engineer to join our ATD team. The candidate should have a strong background in back-end design of ASIC/SoC chips. The ideal candidate will have a bachelor’s or master’s degree in Electrical Engineering or a related field. Requirements: 1 - 2 Years of experience in physical design Bachelor’s or master’s degree in Electrical/Electronics Engineering or a related field Strong understanding of physical design principles Must know the basics of floorplan, placement, CTS, routing, ECO, Physical Verification Proficiency in back-end design tools, such as Cadence Genus/Innovus/Tempus/Voltus Excellent problem-solving skills and attention to detail Effective communication and collaboration skills Responsibilities: Synthesis to GDSII Perform full Physical design flow and its verification Work closely with Digital Design and DFT engineers Ensure...
Hello Dear Readers,
Currently, at Cadence Banglore, Noida vacancy for Design IP Verification Engineer II role.
Job Description:
Design Verification Engineer for IP development team.
- Verification role for Serial and Interface Design IPs verification (PCIe, CCIX, CXL, USB, Ethernet, SATA/SAS, UFS, SPI, HDMI, MIPI, I3C)
- UVM testbench development to build a robust, scalable and efficient testbench to verify the design IPs.
- In addition to UVM functional verification, the role could involve Formal verification of complex design modules.
- In addition to UVM functional verification, role could involve participating in Emulation qualification of design IPs.
- Understand design and produce detailed verification strategy and test plan.
- Self-starter and learner with passion for getting the job done on time with great quality.
- Strong problem solving, analytical and debug skills
- Excellent verbal and written communications skills
- Clearly communicate project status, issues etc.
Position Requirements:
- BE/BTech/ME/MTech - Electrical / Electronics / VLSI with an experience as a design and verification engineer.
- Strong background on functional verification fundamentals, environment planning, test plan generation, environment development is a must.
- Design Verification experience verifying complex designs and leading projects from concept to verification closure.
- Strong hands-on UVM and System Verilog coding experience and functional verification environment development is required.
- Experience working on verifying any Serial IP or Interface protocols (PCIe, CCIX, CXL, USB, Ethernet, SATA/SAS, UFS, SPI, HDMI, MIPI, I3C)
- Formal verification and/or Emulation experience is highly desirable.
- AMBA protocol (AXI5, CHI, CXS) experience is desirable.
- Familiarity with using 3rd party VIPs, Cadence preferred.
- Team player with strong communication skills, and ability to work independently on the verification of a portion of the design.
- Prior experience in IP development teams would be an added advantage.
Comments
Post a Comment