Skip to main content

Product Engineer II at Cadence Design Systems

Hello Dear Readers, Cadence Design Systems has a vacancy for a Product Engineer II role. Cadence is a pivotal leader in electronic design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality.  Cadence customers are the world’s most innovative companies, delivering extraordinary electronic products from chips to boards to systems for the most dynamic market applications including consumer, hyperscale computing, 5G communications, automotive, aerospace industrial and health. The Cadence Advantage: The opportunity to work on cutting-edge technology in an environment that encourages you to be creative, innovative, and to make an impact. Cadence’s employee-friendly policies focus on the physical and mental well-being of employees, career development, providing opportunities for learning, and celebrating success in recog...

RTL FPGA Engineer at Optimized Solutions

  Hello Dear Readers, 

Currently at Optimized Solutions Gandhinagar, Gujarat vacancy for RTL FPGA Engineer role.

About the job:

Design and RTL Coding using Verilog and/ or VHDL, Design Verification FPGA Synthesis, Place & Route, timing verification, Programming Lab-based analysis and debug on Hardware platforms FPGA prototyping .

2-5 Years of Experience in FPGA Design & Development BE/ BTECH/ ME/ MTECH in EC/ EE/ CS or related field Experience of VHDL and/ or Verilog programming languages Exposure to industry std FPGA design tools.

Mandatory Skills:

  • RTL / Logic Development in VHDL/Verilog
  • Full FPGA development flow from logic design, place route, timing analysis closure
  • Experience with advanced Xilinx/Intel FPGA families and the Xilinx/Intel development tools including Vivado/Quartus
  • Making test benches for functional simulation of IP/FPGA design
  • Troubleshooting and debugging FPGA implementations on boards
  • Knowledge of any scripting language such as bash/Perl/python
  • Highly motivated, self-starter with good interpersonal skills and a strong team player
  • Excellent communication, critical thinking, and problem-solving skills

Desired Skills:

  • Sound knowledge and experience of Verilog or VHDL for FPGA based design.
  • Experience of using Xilinx Vitis Unified Software Platform, Vivado design Suit, HLS etc.
  • Experience of using Intel Quartus Prime Design Software and Nios Embedded Design Suite.
  • Experience on Altera/ Xilinx SOC FPGA (Zynq, MPSOC, Stratix/ARRIA SOC etc.).
  • Knowledge of interfaces like High speed ADCs/DACs, PCIe, USB, Ethernet, SerDES Memories like DDR etc.
  • Good Logic ability and Digital Fundamentals.
  • Good general engineering fundamentals.
  • Excellent teamwork and people skills.

Comments

Popular posts from this blog

SDC (Synopsys Design Constraints) contents part 4

Today, we will be discussing the remaining constraints mentioned in the SDC, which pertain to timing exceptions and design rules. This is the final part of the SDC contents. This is going to be interesting, especially with multicycle paths. Take time to read and try to comprehend. 10. set_max_transition     By setting max transition value, our design checks that all ports and pins are meeting the specified limits mentioned in SDC. If these are not satisfied then timing report will give DRVs (design rule violations) in terms of slack. This is specified as               set_max_transition 0.5  UBUF1/A setting maximum limit of 500ps on pin A of Buffer1. 11. set_max_capacitance     This is same as max transition, setting the maximum capacitance value. if our design not meeting this value then violation will occur. This will also reports under design rule violations in terms of slack.     set_max_capacitance 0.7 [all_...

Apprenticeship CAI at MediaTek Bangalore

Hello Dear Readers,   Currently at MediaTek Bangalore vacancy for an Apprenticeship CAI role. Job Description: B.Tech degree in Electrical/Electronics Engineering with a strong educational background in Digital circuit design Experience in physical design of high performance design with frequencies > 2 Ghz. Experienced in hierarchical design, budgeting, multiple voltage domains and multiple clock domains. Strong skills with Cadence Encounter. Solid understanding of STA and timing constraints. Experienced in working on advanced process nodes (16nm). Strong expertise in Physical Verification to debug LVS/DRC issues at the block level. Requirement: B.Tech degree in Electrical/Electronics Engineering with strong educational background in Digital circuit design Experience in physical design of high performance design with frequencies > 2 Ghz. Experienced in hierarchical design, budgeting, multiple voltage domains and multiple clock domains. Strong skills with Cadence Enc...

IC Physical Design (PnR) at Ulkasemi

Hello Dear Readers,   Ulkasemi  has a vacancy for an IC Physical Design (PnR) role. Job Overview: As a full-time Trainee Engineer, the individual will be working on IC Physical Design implementation from RTL to GDSII to create design databases ready for manufacturing with a special focus on power, performance & area optimization with next-generation state-of-the-art process technologies. Job Responsibilities: Perform physical design implementation which includes Floor planning, Power Planning, Clock Tree Synthesis, Place and Route, ECO, Logic Equivalence checks Timing analysis, physical & electrical verification, driving the sign-off closure meeting schedule, and design goals Develop flow, methodologies, and automation scripts for various implementation steps Follow the instructions, compile documents, prepare deliverables, and report to the team lead Should remain up to date with the latest technology trends Educational Qualification:   B.Sc/M.Sc   in EEE or...