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Senior Eng CAD Engineering at Global Foundries

Hello Dear Readers,   Currently at Global Foundries, vacancy for Senior Eng CAD Engineering role. About GlobalFoundries: GlobalFoundries is a leading full-service semiconductor foundry providing a unique combination of design, development, and fabrication services to some of the world’s most inspired technology companies. With a global manufacturing footprint spanning three continents, GlobalFoundries makes possible the technologies and systems that transform industries and give customers the power to shape their markets. For more information, visit www.gf.com. Introduction: Technology Computer Aided Design tools are critical to accelerate the technology development and deployment in our Fabs. We are seeking to strengthen our TCAD team with highly motivated Individuals who are at the early phase of their career. The candidate brings passion for semiconductor technologies and devices, strives for high-quality work, cares about details, and is willing to learn and cooperate in a...
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GPU Implementation Engineer at Qualcomm

  Hello Dear Readers,

Currently at Qualcomm Bangalore vacancy for GPU Implementation Engineer role.

Job Area:

Engineering Group, Engineering Group > Hardware Engineering

General Summary:

  • Participate in the development of ASICs, with emphasis in Constraint development, Synthesis, Static Timing Analysis (STA), Power Estimation and driving clock tree synthesis.
  • Create design of experiments and do detailed PPA comparison analysis to improve quality of results, tuning recipes and setting course for the projects going forward.
  • Work closely with RTL design, DFT, PD Implementation, Power  teams to optimize Performance, Power and Area (PPA) for best PPA
  • Proficient in constraint generation and validation.
  • Tabulate metrics results for analysis comparison.
  • Develop Rapid Physical synthesis Convergence Methodologies and Automation for optimal PPA.
  • Help all team members in resolving their technical queries and keep project on track.
  • Develop new flow and methodologies to keep improving QOR.

Minimum Qualifications:

  • 1-3 years of experience in ASIC Physical synthesis/STA
  • Expertise in Synopsys/Cadence Synthesis tools
  • Expertise with STA with prime time/Tempus.
  • Good Experience in synthesis timing closure and interactions with DFT and PD.
  • Expertise in Low power flows for CLP, UPF ( Cadence low power, Unified power format)
  • Experience in formal verification with Cadence LEC
  • Expertise in ECO flows using conformal/Formality ECO.
  • Experience in Spyglass Lint/CDC checks and waiver creation
  • Experience in RTL HDL languages Verilog/VHDL.
  • Understanding of RTL to GDS flow
  • Expertise in Perl, TCL language
  • Excellent collaboration skill with all stakeholders is a must.
  • Excellent communication skills are a must.

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