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RTL Design Engineer at Skyroot Aerospace

Hello, Dear Readers, Skyroot Aerospace has a vacancy for the RTL Design Engineer role. About Skyroot Aerospace: A cutting-edge startup founded by ex-ISRO scientists. Dedicated to affordable space access, we're rewriting aerospace technology rules. Our dynamic team fosters inventiveness, collaboration, and relentless excellence. Join us on a transformative journey to redefine space possibilities. Welcome to the forefront of space innovation with Skyroot Aerospace! Purpose of role: Understand architectural requirements and Design micro-architecture, implement design blocks using VHDL/Verilog for FPGA based Avionics packages for orbital launch vehicles and ground infrastructure. Job Requirements: 2+ Years of RTL and system design experience. Strong knowledge on Digital System Design (DSD). Strong knowledge of RTL/SoC design/integration with VHDL/Verilog. Strong knowledge in problem solving and debugging skills. Ability to understand architectural requirements and Design micro-archite...
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GPU Implementation Engineer at Qualcomm

  Hello Dear Readers,

Currently at Qualcomm Bangalore vacancy for GPU Implementation Engineer role.

Job Area:

Engineering Group, Engineering Group > Hardware Engineering

General Summary:

  • Participate in the development of ASICs, with emphasis in Constraint development, Synthesis, Static Timing Analysis (STA), Power Estimation and driving clock tree synthesis.
  • Create design of experiments and do detailed PPA comparison analysis to improve quality of results, tuning recipes and setting course for the projects going forward.
  • Work closely with RTL design, DFT, PD Implementation, Power  teams to optimize Performance, Power and Area (PPA) for best PPA
  • Proficient in constraint generation and validation.
  • Tabulate metrics results for analysis comparison.
  • Develop Rapid Physical synthesis Convergence Methodologies and Automation for optimal PPA.
  • Help all team members in resolving their technical queries and keep project on track.
  • Develop new flow and methodologies to keep improving QOR.

Minimum Qualifications:

  • 1-3 years of experience in ASIC Physical synthesis/STA
  • Expertise in Synopsys/Cadence Synthesis tools
  • Expertise with STA with prime time/Tempus.
  • Good Experience in synthesis timing closure and interactions with DFT and PD.
  • Expertise in Low power flows for CLP, UPF ( Cadence low power, Unified power format)
  • Experience in formal verification with Cadence LEC
  • Expertise in ECO flows using conformal/Formality ECO.
  • Experience in Spyglass Lint/CDC checks and waiver creation
  • Experience in RTL HDL languages Verilog/VHDL.
  • Understanding of RTL to GDS flow
  • Expertise in Perl, TCL language
  • Excellent collaboration skill with all stakeholders is a must.
  • Excellent communication skills are a must.

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