Hello Dear Readers, At Applied Materials Bangalore, there is a vacancy for a Physical Design/PDK methodology Engineer role. Applied Materials is a global leader in materials engineering solutions used to produce virtually every new chip and advanced display in the world. We design, build and service cutting-edge equipment that helps our customers manufacture display and semiconductor chips – the brains of devices we use every day. As the foundation of the global electronics industry, Applied enables the exciting technologies that literally connect our world – like AI and IoT. If you want to push the boundaries of materials science and engineering to create next generation technology, join us to deliver material innovation that changes the world. Key Responsibility: Expertise in PDK enablement and library validation/automation. Hands-on experience with LVS/Parasitic extraction/standard cell characterization flows and methodologies Design/System level experience with DTCO and ...
Hello Dear Readers,
Currently at Qualcomm Bangalore vacancy for GPU Implementation Engineer role.
Job Area:
Engineering Group, Engineering Group > Hardware Engineering
General Summary:
- Participate in the development of ASICs, with emphasis in Constraint development, Synthesis, Static Timing Analysis (STA), Power Estimation and driving clock tree synthesis.
- Create design of experiments and do detailed PPA comparison analysis to improve quality of results, tuning recipes and setting course for the projects going forward.
- Work closely with RTL design, DFT, PD Implementation, Power teams to optimize Performance, Power and Area (PPA) for best PPA
- Proficient in constraint generation and validation.
- Tabulate metrics results for analysis comparison.
- Develop Rapid Physical synthesis Convergence Methodologies and Automation for optimal PPA.
- Help all team members in resolving their technical queries and keep project on track.
- Develop new flow and methodologies to keep improving QOR.
Minimum Qualifications:
- 1-3 years of experience in ASIC Physical synthesis/STA
- Expertise in Synopsys/Cadence Synthesis tools
- Expertise with STA with prime time/Tempus.
- Good Experience in synthesis timing closure and interactions with DFT and PD.
- Expertise in Low power flows for CLP, UPF ( Cadence low power, Unified power format)
- Experience in formal verification with Cadence LEC
- Expertise in ECO flows using conformal/Formality ECO.
- Experience in Spyglass Lint/CDC checks and waiver creation
- Experience in RTL HDL languages Verilog/VHDL.
- Understanding of RTL to GDS flow
- Expertise in Perl, TCL language
- Excellent collaboration skill with all stakeholders is a must.
- Excellent communication skills are a must.
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