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SoC RTL Design Engineer at Texas Instruments

  Hello Dear Readers, At Texas Instruments Bangalore, there is a vacancy for SoC RTL Design Engineer role. Are you looking for a career at one of the leading semiconductor companies in the world Texas Instruments (TI) is looking for a SoC RTL Design Engineer to join the team of enthusiastic engineers who develops highly complex mixed signal devices for audio applications with industry leading performance. These audio products are truly mixed-signal devices with highly integrated digital circuits such as a DSP core for digital filters and audio signal processing blocks, hardware processing blocks, analog controllers, various serial interfaces (Audio serial interfaces, I2C, SPI) and other digital blocks like clock-generation, registers map, Interrupts etc. This is a great opportunity to be part of an established team that’s continuing to look for growth opportunities, working with worldwide leading customers and developing cutting edge solutions in the areas of consumer electr...
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GPU Implementation Engineer at Qualcomm

  Hello Dear Readers,

Currently at Qualcomm Bangalore vacancy for GPU Implementation Engineer role.

Job Area:

Engineering Group, Engineering Group > Hardware Engineering

General Summary:

  • Participate in the development of ASICs, with emphasis in Constraint development, Synthesis, Static Timing Analysis (STA), Power Estimation and driving clock tree synthesis.
  • Create design of experiments and do detailed PPA comparison analysis to improve quality of results, tuning recipes and setting course for the projects going forward.
  • Work closely with RTL design, DFT, PD Implementation, Power  teams to optimize Performance, Power and Area (PPA) for best PPA
  • Proficient in constraint generation and validation.
  • Tabulate metrics results for analysis comparison.
  • Develop Rapid Physical synthesis Convergence Methodologies and Automation for optimal PPA.
  • Help all team members in resolving their technical queries and keep project on track.
  • Develop new flow and methodologies to keep improving QOR.

Minimum Qualifications:

  • 1-3 years of experience in ASIC Physical synthesis/STA
  • Expertise in Synopsys/Cadence Synthesis tools
  • Expertise with STA with prime time/Tempus.
  • Good Experience in synthesis timing closure and interactions with DFT and PD.
  • Expertise in Low power flows for CLP, UPF ( Cadence low power, Unified power format)
  • Experience in formal verification with Cadence LEC
  • Expertise in ECO flows using conformal/Formality ECO.
  • Experience in Spyglass Lint/CDC checks and waiver creation
  • Experience in RTL HDL languages Verilog/VHDL.
  • Understanding of RTL to GDS flow
  • Expertise in Perl, TCL language
  • Excellent collaboration skill with all stakeholders is a must.
  • Excellent communication skills are a must.

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