Hello Dear Readers, Currently at Dew Software Bangalore vacancy for Design Engineer - STA, SD, Power, PDN role. Dew Software, a leading player in the Digital Transformation space, is seeking a skilled Design Engineer specializing in STA (Static Timing Analysis), SD (Signal Integrity), Power, and PDN (Power Delivery Network) to join our team. Working with Fortune 500 companies to support their digital innovation and transformation strategies, the Design Engineer will be responsible for ensuring the integrity and efficiency of digital designs through comprehensive analysis and optimization. Dew Software is dedicated to delivering exceptional outcomes with cutting-edge technologies, and this is an excellent opportunity to contribute to the growth and success of our clients. Responsibilities: Perform STA (Static Timing Analysis) to ensure design meets timing requirements Conduct signal integrity analysis to optimize signal integrity and minimize signal integrity issues Provide power anal
Hello Dear Readers,
Currently at Qualcomm Bangalore vacancy for GPU Implementation Engineer role.
Job Area:
Engineering Group, Engineering Group > Hardware Engineering
General Summary:
- Participate in the development of ASICs, with emphasis in Constraint development, Synthesis, Static Timing Analysis (STA), Power Estimation and driving clock tree synthesis.
- Create design of experiments and do detailed PPA comparison analysis to improve quality of results, tuning recipes and setting course for the projects going forward.
- Work closely with RTL design, DFT, PD Implementation, Power teams to optimize Performance, Power and Area (PPA) for best PPA
- Proficient in constraint generation and validation.
- Tabulate metrics results for analysis comparison.
- Develop Rapid Physical synthesis Convergence Methodologies and Automation for optimal PPA.
- Help all team members in resolving their technical queries and keep project on track.
- Develop new flow and methodologies to keep improving QOR.
Minimum Qualifications:
- 1-3 years of experience in ASIC Physical synthesis/STA
- Expertise in Synopsys/Cadence Synthesis tools
- Expertise with STA with prime time/Tempus.
- Good Experience in synthesis timing closure and interactions with DFT and PD.
- Expertise in Low power flows for CLP, UPF ( Cadence low power, Unified power format)
- Experience in formal verification with Cadence LEC
- Expertise in ECO flows using conformal/Formality ECO.
- Experience in Spyglass Lint/CDC checks and waiver creation
- Experience in RTL HDL languages Verilog/VHDL.
- Understanding of RTL to GDS flow
- Expertise in Perl, TCL language
- Excellent collaboration skill with all stakeholders is a must.
- Excellent communication skills are a must.
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