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Showing posts from July, 2021

Physical Design/PDK methodology Engineer

Hello Dear Readers, At Applied Materials Bangalore, there is a vacancy for a Physical Design/PDK methodology Engineer role. Applied Materials is a global leader in materials engineering solutions used to produce virtually every new chip and advanced display in the world. We design, build and service cutting-edge equipment that helps our customers manufacture display and semiconductor chips – the brains of devices we use every day. As the foundation of the global electronics industry, Applied enables the exciting technologies that literally connect our world – like AI and IoT. If you want to push the boundaries of materials science and engineering to create next generation technology, join us to deliver material innovation that changes the world.  Key Responsibility: Expertise in PDK enablement and library  validation/automation. Hands-on experience with LVS/Parasitic extraction/standard cell characterization flows and methodologies Design/System level experience with DTCO and ...
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Internally Generated Clocks & Gated Clocks Modelling Using Verilog HDL

  Hello Dear Readers, Today, I will explain how one can modeling an Internally and Gated clock using Verilog HDL. 1).  Internally Generated Clocks: Internally generated clock signals use a system or master clock and generate output as an internally generated clock signal. But, internally generated clock signals need to be avoided as it causes the functional and timing issues in the design. The functional and timing problems are due to the combinational logic propagation delays. The internally generated clock signals can generate a glitch or spike in the output. This can trigger the sequential logic multiple times or can generate undesired output. Even due to violation of setup or hold time these types of designs have timing violations. It is always recommended to generate the internal clocks by using register output logic. But still due to the propagation delay of the flip-flop, the overall cumulative delay or skew can generate glitches or spikes in the design. As shown b...
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Different types of Counters In Verilog HDL

  Hello Dear Readers, Today, I will explain Designing of the different types of counters. There are two types of counter based on the how clock signal is assigned to it namely 1). Synchronous Counters 2). Asynchronous Counter.  1). Synchronous Counters: If all the storage elements are triggered by the same source clock signal then the design is said to be synchronous. The advantage of the synchronous design is the overall propagation delay for the design is equal to the propagation delay of the flip-flop or storage element. STA is very easy for the synchronous logic and even performance improvement is possible by using the pipelining. Most of the ASIC implementation uses synchronous logic. In practical applications counters are used as a clock divider network. Even counters are used in the frequency synthesizers to generate variable frequency outputs. i) Parameterized N Bit  Up Counter: Counters are used to generate the predefined and required count sequence on the a...
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SOI Technology-Introduction to Basics

  Hello Dear Readers, Today, I will explain SOI Technology in VLSI and how much it influences the VLSI Industry. Silicon-on-insulator (SOI) , has been used for various applications, such as radiation-hardened circuits, since the 1970s. Recent developments have brought CMOS SOI into the limelight again, this time because of the potential for high-speed design operations. Silicon-on-insulator (SOI) is a "non-bulk" technology that builds transistors on top of an insulating layer instead of in a semiconductor substrate. This reduces parasitic capacitance levels and yields higher-speed operation, but it introduces a class of problems of its own. Early SOI technologies used crystals, such as sapphire (silicon-on-sapphire or SOS), as an insulating substrate. Sapphire was used because its lattice constant (the distance between neighboring atoms) is close to that of silicon, and thin layers of device-grade crystalline silicon can be grown on it. Unfortunately, Sapphire and other like...
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