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Showing posts from July, 2021

VLSI Packaging Evolution and Innovations

Hello Dear Readers,   Today in this post, I will provide some deep insight into the VLSI packaging evolution and innovations. Semiconductor packaging has evolved from a simple protective housing into a critical performance enabler. In the modern VLSI landscape, packaging is no longer an afterthought; it is a fundamental determinant of PPA (Power, Performance, and Area) metrics, often dictating the thermal limits and signal integrity of the final SoC. 1. Traditional Packaging Technologies: These methods are the workhorses of the industry, widely used for low-to-medium complexity devices where cost-efficiency is paramount. Wire Bonding (QFN, QFP, DIP): Wire bonding is the most mature interconnection technology. It uses thin gold, copper, or aluminum wires to connect the die's bond pads to the package's internal leadframe. Implementation: The die is attached face-up to a leadframe or substrate. A wire bonder uses thermocompression or ultrasonic energy to attach wires betwee...
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Internally Generated Clocks & Gated Clocks Modelling Using Verilog HDL

  Hello Dear Readers, Today, I will explain how one can modeling an Internally and Gated clock using Verilog HDL. 1).  Internally Generated Clocks: Internally generated clock signals use a system or master clock and generate output as an internally generated clock signal. But, internally generated clock signals need to be avoided as it causes the functional and timing issues in the design. The functional and timing problems are due to the combinational logic propagation delays. The internally generated clock signals can generate a glitch or spike in the output. This can trigger the sequential logic multiple times or can generate undesired output. Even due to violation of setup or hold time these types of designs have timing violations. It is always recommended to generate the internal clocks by using register output logic. But still due to the propagation delay of the flip-flop, the overall cumulative delay or skew can generate glitches or spikes in the design. As shown b...
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Different types of Counters In Verilog HDL

  Hello Dear Readers, Today, I will explain Designing of the different types of counters. There are two types of counter based on the how clock signal is assigned to it namely 1). Synchronous Counters 2). Asynchronous Counter.  1). Synchronous Counters: If all the storage elements are triggered by the same source clock signal then the design is said to be synchronous. The advantage of the synchronous design is the overall propagation delay for the design is equal to the propagation delay of the flip-flop or storage element. STA is very easy for the synchronous logic and even performance improvement is possible by using the pipelining. Most of the ASIC implementation uses synchronous logic. In practical applications counters are used as a clock divider network. Even counters are used in the frequency synthesizers to generate variable frequency outputs. i) Parameterized N Bit  Up Counter: Counters are used to generate the predefined and required count sequence on the a...
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SOI Technology-Introduction to Basics

  Hello Dear Readers, Today, I will explain SOI Technology in VLSI and how much it influences the VLSI Industry. Silicon-on-insulator (SOI) , has been used for various applications, such as radiation-hardened circuits, since the 1970s. Recent developments have brought CMOS SOI into the limelight again, this time because of the potential for high-speed design operations. Silicon-on-insulator (SOI) is a "non-bulk" technology that builds transistors on top of an insulating layer instead of in a semiconductor substrate. This reduces parasitic capacitance levels and yields higher-speed operation, but it introduces a class of problems of its own. Early SOI technologies used crystals, such as sapphire (silicon-on-sapphire or SOS), as an insulating substrate. Sapphire was used because its lattice constant (the distance between neighboring atoms) is close to that of silicon, and thin layers of device-grade crystalline silicon can be grown on it. Unfortunately, Sapphire and other like...
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