Hello Dear Readers, Currently at Dew Software Bangalore vacancy for Design Engineer - STA, SD, Power, PDN role. Dew Software, a leading player in the Digital Transformation space, is seeking a skilled Design Engineer specializing in STA (Static Timing Analysis), SD (Signal Integrity), Power, and PDN (Power Delivery Network) to join our team. Working with Fortune 500 companies to support their digital innovation and transformation strategies, the Design Engineer will be responsible for ensuring the integrity and efficiency of digital designs through comprehensive analysis and optimization. Dew Software is dedicated to delivering exceptional outcomes with cutting-edge technologies, and this is an excellent opportunity to contribute to the growth and success of our clients. Responsibilities: Perform STA (Static Timing Analysis) to ensure design meets timing requirements Conduct signal integrity analysis to optimize signal integrity and minimize signal integrity issues Provide power anal
Hello Dear Readers, Currently, at BITSILICA Hyderabad vacancy for a Design Verification Engineer role. Company: BITSILICA BITSILICA is the fastest growing global Semiconductor Design Services Company, supporting clients in developing complex ASIC/SoCs with our team of 200+ engineers in VLSI, Embedded Systems & AI/ML, etc. Job Title: Design Verification Engineer FLSA: Full time Location: Bangalore/Hyderabad Job Requirements: Qualification: BE /B-Tech/ M-Tech in Electronics/Electrical/Computer Science Experience: 0-3 Years Availability: Immediate Skills expertise: • Strong knowledge on Verilog HDL, Digital Design, and System Verilog. • Developing or maintaining UVM testbenches and its associated components • Writing & analysing functional coverage, assertions • Strong Protocol exposure on AMBA Bus interfaces (AXI, AHB, APB) • Good to have understanding of Ethernet/USB/PCIe/NVMe/CXL/QSPI/I2S protocols • Basic Knowledge on C Language, Python or Perl. Soft skills: • Good team play