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Design Engineer - STA, SD, Power, PDN at Dew Software

Hello Dear Readers,   Currently at Dew Software Bangalore vacancy for Design Engineer - STA, SD, Power, PDN role. Dew Software, a leading player in the Digital Transformation space, is seeking a skilled Design Engineer specializing in STA (Static Timing Analysis), SD (Signal Integrity), Power, and PDN (Power Delivery Network) to join our team. Working with Fortune 500 companies to support their digital innovation and transformation strategies, the Design Engineer will be responsible for ensuring the integrity and efficiency of digital designs through comprehensive analysis and optimization. Dew Software is dedicated to delivering exceptional outcomes with cutting-edge technologies, and this is an excellent opportunity to contribute to the growth and success of our clients. Responsibilities: Perform STA (Static Timing Analysis) to ensure design meets timing requirements Conduct signal integrity analysis to optimize signal integrity and minimize signal integrity issues Provide power anal
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ARM Assembly Language Practice Question And Answer Part-1

  Hello Dear Readers,   Today in this post I will provide some basics to advanced ARM's assembly language practice QA I have used the Keil tool for code writing. Q-1).   Perform subtraction of the numbers stored at memory location 0x4000 from the number stored at memory location 0x4004 and place the result in memory location 0x4008. Code: ; Program of the substraction   area into, code, readonly  entry   mov r1, #0x4000   ldr r2,[r1]   ldr r3,[r1, #4]  sub r4,r3,r2 ; perform substraction operation  str r4,[r1, #8] ; store the result at memory location 0x4008  end Output: Q-2).   Write a program to check whether the number stored at the memory location is even or odd. Code: ; program for identity number is even or odd area prog2, code, readonly  entry  mov r1,#0x4000 ; data location  ldr r2,[r1]  tst r2,#1 ; anding with 0x01 will be updating status of flag register  bne odd  mov r1,r2 ; even number stored at r1  odd mov r3,r2 ; store odd number  end  Output: Q-3).  Write  a program
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RTL to GDS-II of FIR Filter Using Open Source Tool Q-flow

   Hello Dear Readers,   Today in this post I will discuss further the  FIR Filter Front-End  implementation at the back-end side by performing the RTL to GDS-II tool Q-flow. For the Installation of the tool follow the steps which are mentioned here below, I have tested my FIR filter Verilog code using Q-flow as shown in Fig. 1 successfully. In which I have selected OSU018 which is 180nm Technology Node. After completing all the steps last one is to click on Edit Layout options will go to us in the Magic tool for displaying the final layout of our RTL code as shown in FIg. 2 where we can see also zero DRC error at top of the middle point. Fig. 1 Q-flow Physical Design Flow Fig. 2 Final Layout of FIR filter Connect with me  1.Linkedln 2.Instagram 3.Facebook
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How FPGA is Programmable ASIC and Its Building Blocks

  Hello Dear Readers,   Today in this post I will discuss how FPGA is a programmable ASIC and what are the basic building blocks of the FPGA. Modern FPGAs are named programmable ASICs and used in various applications which include the ASIC SOC designs and prototyping. FPGA programming includes the following types and is discussed below section. The main programming types for any FPGA are, 1). SRAM Based FPGAs: Most of the FPGAs in the market are based on SRAM technology. They store the configuration bit-file in the SRAM cells designed using latches. As the SRAM is volatile, they need to be configured at the start. There are two modes for programming and they are Master and Slave. The SRAM memory cell is shown in Fig.1. In the Master mode, FPGA reads configuration data from the external source and that can be flash. In the Slave mode, FPGA is configured by using the external master device such as processor. The external configuration interface can be JTAG that is also called as boundary
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Architecting Speed in FPGA

  Hello Dear Readers,   Today in this post we will discuss how the architecting speed inside will be changing by writing efficient RTL coding. Sophisticated tool optimizations are often not good enough to meet most design constraints if an arbitrary coding style is used. Here we will discuss the first of three primary physical characteristics of a digital design speed and also discuss methods for architectural optimization in an FPGA. There are three primary definitions of speed depending on the context of the problem: throughput, latency, and timing. In the context of processing data in an FPGA, throughput refers to the amount of data that is processed per clock cycle. A common metric for throughput in bits per second. Latency refers to the time between data input and processed data output. The typical metric for latency will be time or clock cycles. Timing refers to the logic delays between sequential elements. When we say a design does not “meet timing,” we mean that the delay of th
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