Skip to main content

Posts

VLSI Packaging Evolution and Innovations

Hello Dear Readers,   Today in this post, I will provide some deep insight into the VLSI packaging evolution and innovations. Semiconductor packaging has evolved from a simple protective housing into a critical performance enabler. In the modern VLSI landscape, packaging is no longer an afterthought; it is a fundamental determinant of PPA (Power, Performance, and Area) metrics, often dictating the thermal limits and signal integrity of the final SoC. 1. Traditional Packaging Technologies: These methods are the workhorses of the industry, widely used for low-to-medium complexity devices where cost-efficiency is paramount. Wire Bonding (QFN, QFP, DIP): Wire bonding is the most mature interconnection technology. It uses thin gold, copper, or aluminum wires to connect the die's bond pads to the package's internal leadframe. Implementation: The die is attached face-up to a leadframe or substrate. A wire bonder uses thermocompression or ultrasonic energy to attach wires betwee...
Post a Comment
Read more

Silicon Design Engineer 1 at AMD Hyderabad

   Hello Dear Readers, Currently, at AMD Hyderabad vacancy for Silicon Design Engineer 1 role. Summary:   We care deeply about transforming lives with AMD technology to enrich our industry, our communities and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence, while being direct, humble, collaborative and inclusive of diverse perspectives. This is who we are at our best. One Company. One Team.  AMD together we advance.   JOB Description: B-tech/M-tech fresher Discipline: E&C Apply Here Connect with me  1.Linkedln 2.Instagram 3.Facebook 4.WhatsApp
Post a Comment
Read more

Senior Physical Design Engineer at Samsung Electronics

Hello Dear Readers, Currently, at Samsung Electronics  Bangalore vacancy for a Senior Physical Design Engineer role. About the job: Complex SOC Top Physical Implementation for next generation SoCs in area of mobile application processors, modem sub-systems and connectivity chips by means of Synthesis , Place and Route, STA , timing and physical signoffs  Hands-on experience doing physical design and timing closure of complex blocks and full-chip designs Should have strong understanding of timing, power, and area trade-offs and optimization of PPA Power user of industry-standard tools (ICC/DC/PT/VSLP/Redhawk/Calibre/Formality) and able to understand their capabilities Should have solid understanding of scripting languages such as Perl/Tcl and implementation flows Experience with large SOC designs (>20M gates) with frequencies in excess of 1GHZ . Expertise in block level and full-chip SDC cleanup, Synthesis optimization, Low Power checking and logic equivalence checking ...
Post a Comment
Read more

Graduate Intern Technical at Intel

  Hello Dear Readers, Currently, at Intel  Bangalore vacancy for a Graduate Intern Technical role. Job Description: This description is for intern positions with Intel Labs - Bangalore Design Lab. We are looking for Machine Learning (ML) Research interns to help us create artificial intelligence-based VLSI methodologies/flows. Responsibilities include creating machine learning models, adopting state-of-the-art algorithms, extracting data for training and benchmarking. Your ultimate goal will be to shape and create efficient applications of ML in building chips Qualifications: Preferred qualification: - Ph.D/Master's/Bachelor's Degree in Computer Science or related field- Hands-on experience on Machine Learning Algorithms- Experience with deep learning frameworks- Strong experience in programming and statistics- Excellent verbal and written communication skills- Highly developed attention to detail- Strong presentation skills- Ability to work well in a team environment- Excelle...
Post a Comment
Read more

Best Courses For RTL/FPGA Engineer Profiles

  Hello Dear Readers, Currently, after succeeding up to this today, I will start new NPTEL courses per VLSI and ECE branch job profiles. So let's start with today's RTL/FPGA engineer profiles courses. 1. HARDWARE MODELING USING VERILOG: Coordinators: PROF. INDRANIL SENGUPTA  Department of Computer Science and Engineering IIT Kharagpur INTENDED AUDIENCE: CSE, ECE, EE  PRE-REQUISITES: Basic concepts in digital circuit design, Familiarity with a programming language like C or C++  INDUSTRIES APPLICABLE TO: Intel, Cadence, Mentor Graphics, Synopsys, Xilinx COURSE OUTLINE: The course will introduce the participants to the Verilog hardware description language. It will help them to learn various digital circuit modeling issues using Verilog, writing test benches, and some case studies.  ABOUT INSTRUCTOR:   Prof. Indranil Sengupta has obtained his B.Tech., M.Tech. and Ph.D. degrees in Computer Science and Engineering (CSE) from the University of Calcutta. H...
1 comment
Read more