Hello Dear Readers, At Texas Instruments Bangalore, there is a vacancy for SoC RTL Design Engineer role. Are you looking for a career at one of the leading semiconductor companies in the world Texas Instruments (TI) is looking for a SoC RTL Design Engineer to join the team of enthusiastic engineers who develops highly complex mixed signal devices for audio applications with industry leading performance. These audio products are truly mixed-signal devices with highly integrated digital circuits such as a DSP core for digital filters and audio signal processing blocks, hardware processing blocks, analog controllers, various serial interfaces (Audio serial interfaces, I2C, SPI) and other digital blocks like clock-generation, registers map, Interrupts etc. This is a great opportunity to be part of an established team that’s continuing to look for growth opportunities, working with worldwide leading customers and developing cutting edge solutions in the areas of consumer electr...
Hello Dear Readers, Today in this post I will discuss further the FIR Filter Front-End implementation at the back-end side by performing the RTL to GDS-II tool Q-flow. For the Installation of the tool follow the steps which are mentioned here below, I have tested my FIR filter Verilog code using Q-flow as shown in Fig. 1 successfully. In which I have selected OSU018 which is 180nm Technology Node. After completing all the steps last one is to click on Edit Layout options will go to us in the Magic tool for displaying the final layout of our RTL code as shown in FIg. 2 where we can see also zero DRC error at top of the middle point. Fig. 1 Q-flow Physical Design Flow Fig. 2 Final Layout of FIR filter Connect with me 1.Linkedln 2.Instagram 3.Facebook