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Showing posts from November, 2021

Signal Electromigration (Signal EM): Violations, Examples, and Practical Fixes

  Hello Dear Readers,   Today in this post, I will provide some deep insight into the Signal Electromigration (Signal EM): Violations, Examples, and Practical Fixes. 1. Introduction: As technology nodes shrink into the deep‑submicron and nanometer regime (7nm, 5nm, 3nm and beyond), electromigration (EM) has become a first‑order reliability concern—not only for power/ground (PG) networks but also for signal nets. Signal EM failures are often underestimated because signal currents are transient and bidirectional. However, with higher switching activity, tighter metal pitches, thinner wires, and aggressive timing closure, signal EM can cause latent or early‑life failures if not addressed properly. This article explains: What Signal EM is and how it differs from PG EM Typical Signal EM violation scenarios Detailed, practical examples Root causes behind each violation Proven solutions and best practices to fix and prevent Signal EM issues 2. What is Signal Electromigration: El...

How FPGA is Programmable ASIC and Its Building Blocks

  Hello Dear Readers,   Today in this post I will discuss how FPGA is a programmable ASIC and what are the basic building blocks of the FPGA. Modern FPGAs are named programmable ASICs and used in various applications which include the ASIC SOC designs and prototyping. FPGA programming includes the following types and is discussed below section. The main programming types for any FPGA are, 1). SRAM Based FPGAs: Most of the FPGAs in the market are based on SRAM technology. They store the configuration bit-file in the SRAM cells designed using latches. As the SRAM is volatile, they need to be configured at the start. There are two modes for programming and they are Master and Slave. The SRAM memory cell is shown in Fig.1. In the Master mode, FPGA reads configuration data from the external source and that can be flash. In the Slave mode, FPGA is configured by using the external master device such as processor. The external configuration interface can be JTAG that is also call...