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Design Engineer - STA, SD, Power, PDN at Dew Software

Hello Dear Readers,   Currently at Dew Software Bangalore vacancy for Design Engineer - STA, SD, Power, PDN role. Dew Software, a leading player in the Digital Transformation space, is seeking a skilled Design Engineer specializing in STA (Static Timing Analysis), SD (Signal Integrity), Power, and PDN (Power Delivery Network) to join our team. Working with Fortune 500 companies to support their digital innovation and transformation strategies, the Design Engineer will be responsible for ensuring the integrity and efficiency of digital designs through comprehensive analysis and optimization. Dew Software is dedicated to delivering exceptional outcomes with cutting-edge technologies, and this is an excellent opportunity to contribute to the growth and success of our clients. Responsibilities: Perform STA (Static Timing Analysis) to ensure design meets timing requirements Conduct signal integrity analysis to optimize signal integrity and minimize signal integrity issues Provide power anal
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Silicon Design Engineer 1 at AMD Hyderabad

   Hello Dear Readers, Currently, at AMD Hyderabad vacancy for Silicon Design Engineer 1 role. Summary:   We care deeply about transforming lives with AMD technology to enrich our industry, our communities and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence, while being direct, humble, collaborative and inclusive of diverse perspectives. This is who we are at our best. One Company. One Team.  AMD together we advance.   JOB Description: B-tech/M-tech fresher Discipline: E&C Apply Here Connect with me  1.Linkedln 2.Instagram 3.Facebook 4.WhatsApp
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Senior Physical Design Engineer at Samsung Electronics

Hello Dear Readers, Currently, at Samsung Electronics  Bangalore vacancy for a Senior Physical Design Engineer role. About the job: Complex SOC Top Physical Implementation for next generation SoCs in area of mobile application processors, modem sub-systems and connectivity chips by means of Synthesis , Place and Route, STA , timing and physical signoffs  Hands-on experience doing physical design and timing closure of complex blocks and full-chip designs Should have strong understanding of timing, power, and area trade-offs and optimization of PPA Power user of industry-standard tools (ICC/DC/PT/VSLP/Redhawk/Calibre/Formality) and able to understand their capabilities Should have solid understanding of scripting languages such as Perl/Tcl and implementation flows Experience with large SOC designs (>20M gates) with frequencies in excess of 1GHZ . Expertise in block level and full-chip SDC cleanup, Synthesis optimization, Low Power checking and logic equivalence checking Familiar with
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Graduate Intern Technical at Intel

  Hello Dear Readers, Currently, at Intel  Bangalore vacancy for a Graduate Intern Technical role. Job Description: This description is for intern positions with Intel Labs - Bangalore Design Lab. We are looking for Machine Learning (ML) Research interns to help us create artificial intelligence-based VLSI methodologies/flows. Responsibilities include creating machine learning models, adopting state-of-the-art algorithms, extracting data for training and benchmarking. Your ultimate goal will be to shape and create efficient applications of ML in building chips Qualifications: Preferred qualification: - Ph.D/Master's/Bachelor's Degree in Computer Science or related field- Hands-on experience on Machine Learning Algorithms- Experience with deep learning frameworks- Strong experience in programming and statistics- Excellent verbal and written communication skills- Highly developed attention to detail- Strong presentation skills- Ability to work well in a team environment- Excellen
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Best Courses For RTL/FPGA Engineer Profiles

  Hello Dear Readers, Currently, after succeeding up to this today, I will start new NPTEL courses per VLSI and ECE branch job profiles. So let's start with today's RTL/FPGA engineer profiles courses. 1. HARDWARE MODELING USING VERILOG: Coordinators: PROF. INDRANIL SENGUPTA  Department of Computer Science and Engineering IIT Kharagpur INTENDED AUDIENCE: CSE, ECE, EE  PRE-REQUISITES: Basic concepts in digital circuit design, Familiarity with a programming language like C or C++  INDUSTRIES APPLICABLE TO: Intel, Cadence, Mentor Graphics, Synopsys, Xilinx COURSE OUTLINE: The course will introduce the participants to the Verilog hardware description language. It will help them to learn various digital circuit modeling issues using Verilog, writing test benches, and some case studies.  ABOUT INSTRUCTOR:   Prof. Indranil Sengupta has obtained his B.Tech., M.Tech. and Ph.D. degrees in Computer Science and Engineering (CSE) from the University of Calcutta. He joined the Indian Instit
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