Hello Dear Readers, Texas Instruments Bangalore has a vacancy for the Physical Design Engineer role. We need an Physical Design Methodology Engineer to join our ATD team. The candidate should have a strong background in back-end design of ASIC/SoC chips. The ideal candidate will have a bachelor’s or master’s degree in Electrical Engineering or a related field. Requirements: 1 - 2 Years of experience in physical design Bachelor’s or master’s degree in Electrical/Electronics Engineering or a related field Strong understanding of physical design principles Must know the basics of floorplan, placement, CTS, routing, ECO, Physical Verification Proficiency in back-end design tools, such as Cadence Genus/Innovus/Tempus/Voltus Excellent problem-solving skills and attention to detail Effective communication and collaboration skills Responsibilities: Synthesis to GDSII Perform full Physical design flow and its verification Work closely with Digital Design and DFT engineers Ensure...
Hello Dear Readers, Today in this post I will provide some deep insight into what is happening in the semiconductor industry. So hope you like it and enjoy it to improve your knowledge and awareness about the industry. So let's start it today we are discussing, SpacemiT making significant breakthroughs in RISC-V. SpacemiT develops its first-generation RISC-V fusion computing processor core – the X100. X100 has made significant leaps with its general-purpose and application-oriented fusion computing capabilities. The general-purpose computing performance of the X100 is better than that of the ARM A75 and it outperforms ARM A76 significantly in AI Applications, Vision Applications, and Robot Applications. As a high-performance fusion processor core in RISC-V architecture, the X100 will be used in the production of SpacemiT chips and with application scenarios that have a relatively high demand for computing power. These will include high-performance CPUs, Edge Co...